The present invention relates to a method and structure for forming a field plate in a high voltage array in order to improve the isolation between adjacent cells separated by an isolating area.
In an array of EEPROM cells it is common to have a conducting line of polysilicon crossing the moat of every single cell. This polysilicon overlying a thick field oxide layer is a field transistor with a relatively high threshold voltage. During the WRITE operation this polysilicon line has 16 volts applied to it. Although the field transistor normally has a high threshold voltage it can not be made with a guarantee that it will be higher than 16 volts. Once the field transistor turns on due to the gate voltage on the polysilicon it causes a considerable degradation in the isolation between cells.
A known solution to this problem has been to use a polysilicon field plate connected to the substrate or V.sub.ss underneath the field transistor. Such a structure results in an increase in the cell size because of the space required to run a metal line coupled to all of the polysilicon field plates.
Accordingly, it is a principal object of the invention to provide an improved method and structure for ensuring the field transistor stays turned off and thereby enhancing the isolation between cells. It is a further object of the invention to provide a method for eliminating the separate field plate conducting line used in the prior art and thereby achieve a smaller cell size.